1). Field of the Invention
The embodiments of the invention relates generally to fabrication of semiconductor devices and relates to air-gap-containing metal/insulator interconnect structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI)semiconductor devices and packaging, and more particularly to structures, methods, and materials relating to the incorporation of voids, cavities or air gaps into multiple levels of multilayer interconnect structures for reducing wiring capacitance.
2). Description of the Prior Art
Copper interconnects are formed using a dual damascene process. The incorporation of low-k insulator material may be accomplished by depositing an etch stop layer and a first layer of low-k dielectric material over a copper interconnect. This may be followed by an optional etch stop barrier insulator and then a second layer of low-k material. A via is then etched through the second layer of low-k material, any etch stop barrier insulator, and the first layer of low-k dielectric material to reach the copper interconnect. A trench is then etched into the second layer of low-k material to aid in forming another layer of copper interconnects. Barrier metal and copper are deposited by sputtering, chemical vapor deposition (CVD), electrochemical deposition, or a combination of these methods. The deposited copper, and possibly the barrier metal, will then be planarized using chemical mechanical polishing (CMP) to form copper interconnects.
Air gaps have been used for intra-level insulators for copper, while using silicon oxide or low-k at the inter-level dielectric layers. The air gaps are formed by decomposing sacrificial polymer. However, prior art air gaps can be improved.
The importance of this technical subject is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The more relevant technical developments in the patent literature can be gleaned by considering the following.
US 20020158337 A1—Babich, et al.—Multilayer interconnect structure containing air gaps and method for making—an air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels.
US 20010016412 A1—Lee, Ellis; et al. Interconnect structure with air gap compatible with unlanded vias.
US 20020127844 A1—Grill et al.—Multilevel interconnect structure containing air gaps and method for making.
U.S. Pat. No. 6,495,906 Smith, et al.—Simplified process for producing nanoporous silica—relates to low dielectric constant nanoporous silica films and to processes for their manufacture. A substrate, e.g., a wafer suitable for the production of an integrated circuit, having a plurality of raised lines and/or electronic elements present on its surface, is provided with a relatively high porosity, low dielectric constant, silicon-containing polymer film composition.
U.S. Pat. No. 6,670,022 Wallace, et al.—Nanoporous dielectric films with graded density and process for making such films—relates to nanoporous dielectric films and to a process for their manufacture. A substrate having a plurality of raised lines on its surface is provided with a relatively high porosity, low dielectric constant, silicon containing polymer composition positioned between the raised lines and a relatively low porosity, high dielectric constant, silicon containing composition positioned on the lines.
U.S. Pat. No. 6,423,630 Catabay, et al.—Process for forming low K dielectric material between metal lines—A process is disclosed for forming low k dielectric material between and over a plurality of spaced apart metal lines previously formed over a dielectric layer of an integrated circuit structure.
U.S. Pat. No. 6,642,138 Pan, et al.—Process of making dual damascene structures using a sacrificial polymer—A method is provided to deposit and pattern a sacrificial polymer, and form metal layers. A double hard mask is used to pattern and etch the sacrificial polymer. The double hard mask may be formed at temperatures below 400.degree. C. The sacrificial polymer is capable of being decomposed to become air gaps during annealing.
U.S. Pat. No. 6,342,722 Armacost, et al.—Integrated circuit having air gaps between dielectric and conducting lines.
U.S. Pat. No. 6,423,629—Ahn, et al.—Multilevel copper interconnects with low-k dielectrics and air gaps.